View A28F400BX-B_1998804.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1995 copyright ? intel corporation, 1995 order number: 290501-003 a28f400bx-t/b 4-mbit (256k x16, 512k x8) boot block flash memory family automotive y x8/x16 input/output architecture e a28f400bx-t, A28F400BX-B e for high performance and high integration 16-bit and 32-bit cpus y optimized high density blocked architecture e one 16 kb protected boot block e two 8 kb parameter blocks e one 96 kb main block e three 128 kb main blocks e top or bottom boot locations y extended cycling capability e 1,000 block erase cycles y automated word/byte write and block erase e command user interface e status register e erase suspend capability y sram-compatible write interface y automatic power savings feature e 1 ma typical i cc active current in static operation y very high-performance read e 90 ns maximum access time e 45 ns maximum output enable time y low power consumption e 25 ma typical active read current y deep power-down/reset input e acts as reset for boot operations y automotive temperature operation e b 40 cto a 125 c y write protection for boot block y hardware data protection feature e erase/write lockout during power transitions y industry standard surface mount packaging e jedec rom compatible 44-lead psop y 12v word/byte write and block erase ev pp e 12v g 5% standard y etox tm iii flash technology e 5v read
a28f400bx-t/b intel's 4-mbit flash memory family is an extension of the boot block architecture which includes block- selective erasure, automated write and erase operations and standard microprocessor interface. the 4-mbit flash memory family enhances the boot block architecture by adding more density and blocks, x8/x16 input/ output control, very high speed, low power, an industry standard rom compatible pinout and surface mount packaging. the 4-mbit flash family is an easy upgrade from intel's 2-mbit boot block flash memory family. the intel a28f400bx-t/b are 16-bit wide flash memory offerings optimized to meet the rigorous environmen- tal requirements of automotive applications. these high density flash memories provide user selectable bus operation for either 8-bit or 16-bit applications. the a28f400bx-t and A28F400BX-B are 4,194,304-bit non- volatile memories organized as either 524,288 bytes or 262,144 words of information. they are offered in 44- lead plastic sop packages. the x8/x16 pinout conforms to the industry standard rom/eprom pinout. read and write characteristics are guaranteed over the ambient temperature range of b 40 cto a 125 c. these devices use an integrated command user interface (cui) and write state machine (wsm) for simplified word/byte write and block erasure. the a28f400bx-t provide block locations compatible with intel's mcs-186 family, 80286, i386 tm , i486 tm , i860 tm and 80960ca microprocessors. the A28F400BX-B provides compatibility with intel's 80960kx and 80960sx families as well as other embedded microprocessors. the boot block includes a data protection feature to protect the boot code in critical applications. with a maximum access time of 90 ns, these 4-mbit flash devices are very high performance memories which interface at zero-wait-state to a wide range of microprocessors and microcontrollers. manufactured on intel's 0.8 micron etox tm iii process, the 4-mbit flash memory family provides world class quality, reliability and cost-effectiveness at the 4-mbit density level. 2
a28f400bx-t/b 1.0 product family overview throughout this datasheet the a28f400bx refers to both the a28f400bx-t and A28F400BX-B devices. section 1 provides an overview of the 4-mbit flash memory family including applications, pinouts and pin descriptions. section 2 describes in detail the specific memory organization for the a28f400bx. section 3 provides a description of the family's prin- ciples of operations. finally the family's operating specifications are described. 1.1 main features the a28f400bx boot block flash memory family is a very high performance 4-mbit (4,194,304 bit) memo- ry family organized as either 256-kwords (262,144 words) of 16 bits each or 512-kbytes (524,288 bytes) of 8 bits each. seven separately erasable blocks including a hardware-lockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each) and four main blocks (1 block of 98,304 bytes and 3 blocks of 131,072 bytes) are included on the 4-mbit family. an erase operation erases one of the main blocks in typically 3 seconds and the boot or param- eter blocks in typically 1.5 seconds independent of the remaining blocks. each block can be indepen- dently erased and programmed 1,000 times. the boot block is located at either the top (a28f400bx-t) or the bottom (A28F400BX-B) of the address map in order to accommodate different mi- croprocessor protocols for boot code location. the hardware lockable boot block provides the most secure code storage. the boot block is intended to store the kernel code required for booting-up a sys- tem. when the rp y pin is between 11.4v and 12.6v the boot block is unlocked and program and erase operations can be performed. when the rp y pin is at or below 6.5v the boot block is locked and pro- gram and erase operations to the boot block are ignored. the a28f400bx products are available in the rom/ eprom compatible pinout and housed in the 44-lead psop (plastic small outline) package as shown in figure 3. the command user interface (cui) serves as the interface between the microprocessor or microcon- troller and the internal operation of the a28f400bx flash memory. program and erase automation allows program and erase operations to be executed using a two- write command sequence to the cui. the internal write state machine (wsm) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, there- by unburdening the microprocessor or microcontrol- ler. writing of memory data is performed in word or byte increments typically within 9 m s which is a 100% improvement over previous flash memory products. the status register (sr) indicates the status of the wsm and whether the wsm successfully completed the desired program or erase operation. maximum access time of 90 ns (tacc) is achieved over the automotive temperature range, 10% v cc supply range (4.5v to 5.5v) and 100 pf output load. i pp maximum program current is 40 ma for x16 operation and 30 ma for x8 operation. i pp erase current is 30 ma maximum. v pp erase and pro- gramming voltage is 11.4v to 12.6v (v pp e 12v g 5%) under all operating conditions. typical i cc active current of 25 ma is achieved. the 4-mbit boot block flash memory family is also designed with an automatic power savings (aps) feature to minimize system battery current drain and allows for very low power designs. once the device is accessed to read array data, aps mode will imme- diately put the memory in static mode of operation where i cc active current is typically 1 ma until the next read is initiated. when the ce y and rp y pins are at v cc and the byte y pin is at either v cc or gnd the cmos standby mode is enabled where i cc is typically 80 m a. a deep power-down mode is enabled when the rp y pin is at ground minimizing power consumption and providing write protection during power-up con- ditions. i cc current during deep power-down mode is 50 m a typical . an initial maximum access time or reset time of 300 ns is required from rp y switch- ing until outputs are valid. equivalently, the device has a maximum wake-up time of 210 ns until writes to the command user interface are recognized. when rp y is at ground the wsm is reset, the status register is cleared and the entire device is protected from being written to. this feature pre- vents data corruption and protects the code stored in the device during system reset. the system reset pin can be tied to rp y to reset the memory to nor- mal read mode upon activation of the reset pin. with on-chip program/erase automation in the 4-mbit family and the rp y functionality for data pro- tection, when the cpu is reset and even if a program or erase command is issued, the device will not rec- ognize any operation until rp y returns to its normal state. 3
a28f400bx-t/b for the a28f400bx, byte-wide or word-wide in- put/output control is possible by controlling the byte y pin. when the byte y pin is at a logic low the device is in the byte-wide mode (x8) and data is read and written through dq [ 0:7 ] . during the byte- wide mode, dq [ 8:14 ] are tri-stated and dq15/a-1 becomes the lowest order address pin. when the byte y pin is at a logic high the device is in the word-wide mode (x16) and data is read and written through dq [ 0:15 ] . 1.2 applications the 4-mbit boot block flash memory family com- bines high density, high performance, cost-effective flash memories with blocking and hardware protec- tion capabilities. its flexibility and versatility will re- duce costs throughout the product life cycle. flash memory is ideal for just-in-time production flow, re- ducing system inventory and costs, and eliminating component handling during the production phase. during the product life cycle, when code updates or feature enhancements become necessary, flash memory will reduce the update costs by allowing ei- ther a user-performed code change via floppy disk or a remote code change via a serial link. the 4-mbit boot block flash memory family provides full func- tion, blocked flash memories suitable for a wide range of automotive applications. 4
a28f400bx-t/b 290501 1 figure 1. a28f400bx interface to 8xc196kc 5
a28f400bx-t/b 1.3 pinouts the a28f400bx 44-lead psop pinout follows the industry standard rom/eprom pinout as shown in figure 2. 27c400 nc nc a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ce y gnd oe y dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 290501 3 27c400 nc nc a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 byte y /v pp gnd dq 15 /a b 1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc figure 2. psop lead configuration 6
a28f400bx-t/b 1.4 a28f400bx pin descriptions symbol type name and function a 0 a 17 i address inputs for memory addresses. addresses are internally latched during a write cycle. a 9 i address input: when a 9 is at 12v the signature mode is accessed. during this mode a 0 decodes between the manufacturer and device id's. when byte y is at a logic low only the lower byte of the signatures are read. dq 15 /a b 1 is a don't care in the signature mode when byte y is low. dq 0 dq 7 i/o data inputs/outputs: inputs array data on the second ce y and we y cycle during a program command. inputs commands to the command user interface when ce y and we y are active. data is internally latched during the write and program cycles. outputs array, intelligent identifier and status register data. the data pins float to tri-state when the chip is deselected or the outputs are disabled. dq 8 dq 15 i/o data inputs/outputs: inputs array data on the second ce y and we y cycle during a program command. data is internally latched during the write and program cycles. outputs array data. the data pins float to tri-state when the chip is deselected or the outputs are disabled as in the byte-wide mode (byte y e ``0''). in the byte-wide mode dq 15 /a b 1 becomes the lowest order address for data output on dq 0 -dq 7 . ce y i chip enable: activates the device's control logic, input buffers, decoders and sense amplifiers. ce y is active low; ce y high deselects the memory device and reduces power consumption to standby levels. if ce y and rp y are high, but not at a cmos high level, the standby current will increase due to current flow through the ce y and rp y input stages. rp y i reset/power-down: provides three-state control. puts the device in deep power-down mode. locks the boot block from program/erase. when rp y is at logic high level and equals 6.5v maximum the boot block is locked and cannot be programmed or erased. when rp y e 11.4v minimum the boot block is unlocked and can be programmed or erased. when rp y is at a logic low level the boot block is locked, the deep power-down mode is enabled and the wsm is reset preventing any blocks from being programmed or erased, therefore providing data protection during power transitions. when rp y transitions from logic low to logic high the flash memory enters the read array mode. oe y i output enable: gates the device's outputs through the data buffers during a read cycle. oe y is active low. we y i write enable: controls writes to the command register and array blocks. we y is active low. addresses and data are latched on the rising edge of the we y pulse. byte y i byte y enable: controls whether the device operates in the byte-wide mode (x8) or the word-wide mode (x16). byte y pin must be controlled at cmos levels to meet 130 m a cmos current in the standby mode. byte y e ``0'' enables the byte-wide mode, where data is read and programmed on dq 0 dq 7 and dq 15 /a b 1 becomes the lowest order address that decodes between the upper and lower byte. dq 8 dq 14 are tri-stated during the byte- wide mode. byte y e ``1'' enables the word-wide mode where data is read and programmed on dq 0 dq 15 . v pp program/erase power supply: for erasing memory array blocks or programming data in each block. note: v pp k v pplmax memory contents cannot be altered. v cc device power supply (5v g 10%) gnd ground: for all internal circuitry. nc no connect: pin may be driven or left floating. du don't use pin: pin should not be connected to anything. 7
a28f400bx-t/b 2.0 a28f400bx word/byte-wide products description figure 3. a28f400bx word/byte block diagram 290501 4 8
a28f400bx-t/b 2.1 a28f400bx memory organization 2.1.1 blocking the a28f400bx uses a blocked array architecture to provide independent erasure of memory blocks. a block is erased independently of other blocks in the array when an address is given within the block ad- dress range and the erase setup and erase confirm commands are written to the cui. the a28f400bx is a random read/write memory, only erasure is per- formed by block. 2.1.1.1 boot block operation and data protection the 16-kbyte boot block provides a lock feature for secure code storage. the intent of the boot block is to provide a secure storage area for the kernel code that is required to boot a system in the event of pow- er failure or other disruption during code update. this lock feature ensures absolute data integrity by preventing the boot block from being written or erased when rp y is not at 12v. the boot block can be erased and written when rp y is held at 12v for the duration of the erase or program operation. this allows customers to change the boot code when necessary while providing security when needed. see the block memory map section for address lo- cations of the boot block for the a28f400bx-t and A28F400BX-B. 2.1.1.2 parameter block operation the a28f400bx has 2 parameter blocks (8 kbytes each). the parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic information. the pa- rameter blocks can also be used to store additional boot or main code. the parameter blocks however, do not have the hardware write protection feature that the boot block has. the parameter blocks pro- vide for more efficient memory utilization when deal- ing with parameter changes versus regularly blocked devices. see the block memory map section for ad- dress locations of the parameter blocks for the a28f400bx-t and A28F400BX-B. 2.1.1.3 main block operation four main blocks of memory exist on the a28f400bx (3 x 128 kbyte blocks an d 1 x 96-kbyte blocks). see the following section on block memory map for the address location of these blocks for the a28f400bx-t and A28F400BX-B products. 2.1.2 block memory map two versions of the a28f400bx product exist to support two different memory maps of the array blocks in order to accommodate different microproc- essor protocols for boot code location. the a28f400bx-t memory map is inverted from the A28F400BX-B memory map. 2.1.2.1. A28F400BX-B memory map the A28F400BX-B device has the 16-kbyte boot block located from 00000h to 01fffh to accommo- date those microprocessors that boot from the bot- tom of the address map at 00000h. in the A28F400BX-B the first 8-kbyte parameter block re- sides in memory space from 02000h to 02fffh. the second 8-kbyte parameter block resides in memory space from 03000h to 03fffh. the 96- kbyte main block resides in memory space from 04000h to 0ffffh. the three 128-kbyte main block resides in memory space from 10000h to 1ffffh, 20000h to 2ffffh and 30000h to 3ffffh (word locations). see figure 4. (word addresses) 3ffffh 128-kbyte main block 2ffffh 30000h 128-kbyte main block 1ffffh 20000h 128-kbyte main block 0ffffh 10000h 96-kbyte main block 03fffh 04000h 8-kbyte parameter block 02fffh 03000h 8-kbyte parameter block 01fffh 02000h 16-kbyte boot block 00000h figure 4. A28F400BX-B memory map 9
a28f400bx-t/b 2.1.2.2 a28f400bx-t memory map the a28f400bx-t device has the 16-kbyte boot block located from 3e000h to 3ffffh to accommo- date those microprocessors that boot from the top of the address map. in the a28f400bx-t the first 8-kbyte parameter block resides in memory space from 3d000h to 3dfffh. the second 8-kbyte pa- rameter block resides in memory space from 3c000h to 3cfffh. the 96-kbyte main block re- sides in memory space from 30000h to 3bfffh. the three 128-kbyte main blocks reside in memory space from 20000h to 2ffffh, 10000h to 1ffffh and 00000h to 0ffffh as shown below in figure 5. (word addresses) 3ffffh 16-kbyte boot block 3dfffh 3e000h 8-kbyte parameter block 3cfffh 3d000h 8-kbyte parameter block 3bfffh 3c000h 96-kbyte main block 2ffffh 30000h 128-kbyte main block 1ffffh 20000h 128-kbyte main block 0ffffh 10000h 128-kbyte main block 00000h figure 5. a28f400bx-t memory map 3.0 product family principles of operation flash memory augments eprom functionality with in-circuit electrical write and erase. the 4-mbit flash family utilizes a command user interface (cui) and internally generated and timed algorithms to simplify write and erase operations. the cui allows for 100% ttl-level control inputs, fixed power supplies during erasure and program- ming, and maximum eprom compatibility. in the absence of high voltage on the v pp pin, the 4-mbit boot block flash family will only successfully execute the following commands: read array, read status register, clear status register and intelli- gent identifier mode. the device provides standard eprom read, standby and output disable opera- tions. manufacturer identification and device identi- fication data can be accessed through the cui or through the standard eprom a 9 high voltage ac- cess (v id ) for prom programming equipment. the same eprom read, standby and output disable functions are available when high voltage is applied to the v pp pin. in addition, high voltage on v pp al- lows write and erase of the device. all functions as- sociated with altering memory contents: write and erase, intelligent identifier read and read status are accessed via the cui. the purpose of the write state machine (wsm) is to completely automate the write and erasure of the device. the wsm will begin operation upon receipt of a signal from the cui and will report status back through a status register. the cui will handle the we y interface to the data and address latches, as well as system software requests for status while the wsm is in operation. 3.1 bus operations flash memory reads, erases and writes in-system via the local cpu. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 10
a28f400bx-t/b table 1. bus operations for word-wide mode (byte y e v ih ) mode notes rp y ce y oe y we y a 9 a 0 v pp dq 015 read 1, 2, 3 v ih v il v il v ih xx x d out output disable v ih v il v ih v ih x x x high z standby v ih v ih x x x x x high z deep power-down 9 v il x x x x x x high z intelligent identifier (mfr) 4 v ih v il v il v ih v id v il x 0089h intelligent identifier (device) 4, 5 v ih v il v il v ih v id v ih x 4470h 4471h write 6, 7, 8 v ih v il v ih v il xx x d in table 2. bus operations for byte-wide mode (byte e v il ) mode notes rp y ce y oe y we y a 9 a 0 a b 1 v pp dq 07 dq 814 read 1, 2, 3 v ih v il v il v ih xx x xd out high z output disable v ih v il v ih v ih x x x x high z high z standby v ih v ih x x x x x x high z high z deep power-down 9 v il x x x x x x x high z high z intelligent 4 v ih v il v il v ih v id v il x x 89h high z identifier (mfr) intelligent 4, 5 v ih v il v il v ih v id v ih x x 70h high z identifier (device) 71h write 6, 7, 8 v ih v il v ih v il xx x x d in high z notes: 1. refer to dc characteristics. 2. x can be v il ,v ih for control pins and addresses, v ppl or v pph for v pp . 3. see dc characteristics for v ppl ,v pph ,v hh ,v id voltages. 4. manufacturer and device codes may also be accessed via a cui write sequence. a 1 a 17 e x. 5. device id e 4470h for a28f400bx-t and 4471h for A28F400BX-B. 6. refer to table 3 for valid d in during a write operation. 7. command writes for block erase or word/byte write are only executed when v pp e v pph . 8. to write or erase the boot block, hold rp y at v hh . 9. rp y must be at gnd g 0.2v to meet the 80 m a maximum deep power-down current. 3.2 read operations the 4-mbit boot block flash family has three user read modes; array, intelligent identifier, and status register. status register read mode will be dis- cussed in detail in the ``write operations'' section. during power-up conditions (v cc supply ramping), it takes a maximum of 300 ns from when v cc is at 4.5v minimum to valid data on the outputs. 3.2.1 read array if the memory is not in the read array mode, it is necessary to write the appropriate read mode com- mand to the cui. the 4-mbit boot block flash family has three control functions, all of which must be logi- cally active, to obtain data at the outputs. chip-en- able ce y is the device selection control. reset/ power-down, rp y is the device power control. out- put-enable oe y is the data input/output (dq [ 0:15 ] or dq [ 0:7 ] ) direction control and when active is used to drive data from the selected memo- ry on to the i/o bus. 11
a28f400bx-t/b 3.2.1.1 output control with oe y at logic-high level (v ih ), the output from the device is disabled and data input/output pins (dq [ 0:15 ] or dq [ 0:7 ] are tri-stated. data input is then controlled by we y . 3.2.1.2 input control with we y at logic-high level (v ih ), input to the de- vice is disabled. data input/output pins (dq [ 0:15 ] or dq [ 0:7 ] ) are controlled by oe y . 3.2.2 intelligent identifiers the manufacturer and device codes are read via the cui or by taking the a 9 pin to 12v. writing 90h to the cui places the device into intelligent identifier read mode. a read of location 00000h outputs the manufacturer's identification code, 0089h, and loca- tion 00001h outputs the device code; 4470h for a28f400bx-t, 4471h for A28F400BX-B. when byte y is at a logic low only the lower byte of the above signatures is read and dq 15 /a b 1 is a ``don't care'' during intelligent identifier mode. a read array command must be written to the memory to return to the read array mode. 3.3 write operations commands are written to the cui using standard mi- croprocessor write timings. the cui serves as the interface between the microprocessor and the inter- nal chip operation. the cui can decipher read ar- ray, read intelligent identifier, read status register, clear status register, erase and program com- mands. in the event of a read command, the cui simply points the read path at either the array, the intelligent identifier, or the status register depending on the specific read command given. for a program or erase cycle, the cui informs the write state ma- chine that a write or erase has been requested. dur- ing a program cycle, the write state machine will control the program sequences and the cui will only respond to status reads. durlng an erase cycle, the cui will respond to status reads and erase suspend. after the write state machine has completed its task, it will allow the cui to respond to its full com- mand set. the cui will stay in the current command state until the microprocessor issues another com- mand. the cui will successfully initiate an erase or write operation only when v pp is within its voltage range. depending upon the application, the system design- er may choose to make the v pp power supply switchable, available only when memory updates are desired. the system designer can also choose to ``hard-wire'' v pp to 12v. the 4-mbit boot block flash family is designed to accommodateeeither de- sign practice. it is strongly recommended that rp y be tied to logical reset for data protection during unstable cpu reset function as described in the ``product family overview'' section. 3.3.1 boot block write operations in the case of boot block modifications (write and erase), rp y is set to v hh e 12v typically, in addi- tion to v pp at high voltage. however, if rp y is not at v hh when a program or erase operation of the boot block is attempted, the corresponding status register bit (bit 4 for program and bit 5 for erase, refer to table 5 for status regis- ter definitions) is set to indicate the failure to com- plete the operation. 3.3.2 command user interface (cui) the command user interface (cui) serves as the interface to the microprocessor. the cui points the read/write path to the appropriate circuit block as described in the previous section. after the wsm has completed its task, it will set the wsm status bit to a ``1'', which will also allow the cui to respond to its full command set. note that after the wsm has returned control to the cui, the cui will remain in its current state. 3.3.2.1 command set command device mode codes 00 invalid/reserved 10 alternate program setup 20 erase setup 40 program setup 50 clear status register 70 read status register 90 intelligent identifier b0 erase suspend d0 erase resume/erase confirm ff read array 3.3.2.2 command function descriptions device operations are selected by writing specific commands into the cui. table 3 defines the 4-mbit boot block flash family commands. 12
a28f400bx-t/b table 3. command definitions command cycles req'd bus notes first bus cycle second bus cycle 8 operation address data operation address data read array 1 1 write x ffh intelligent identifier 3 2, 4 write x 90h read ia iid read status register 2 3 write x 70h read x srd clear status register 1 write x 50h erase setup/erase confirm 2 5 write ba 20h write ba d0h word/byte write setup/write 2 6, 7 write wa 40h write wa wd erase suspend/erase resume 2 write x b0h write x d0h alternate word/byte 2 6, 7 write wa 10h write wa wd write setup/write notes: 1. bus operations are defined in tables 1, and 2. 2. ia e identifier address: 00h for manufacturer code, 01h for device code. 3. srd e data read from status register. 4. iid e intelligent identifier data. following the intelligent identifier command, two read operations access manufacturer and device codes. 5. ba e address within the block being erased. 6. wa e address to be written. wd e data to be written at location wd. 7. either 40h or 10h commands is valid. 8. when writing commands to the device, the upper data bus [ dq 8 dq 15 ] e x which is either v cc or v ss to avoid burning additional current. invalid/reserved these are unassigned commands. it is not recom- mended that the customer use any command other than the valid commands specified above. intel re- serves the right to redefine these codes for future functions. read array (ffh) this single write command points the read path at the array. if the host cpu performs a ce y /oe y controlled read immediately following a two-write se- quence that started the wsm, then the device will output status register contents. if the read array command is given after erase setup the device is reset to read the array. a two read array command sequence (ffh) is required to reset to read array after program setup. intelligent identifier (90h) after this command is executed, the cui points the output path to the intelligent identifier circuits. only intelligent identifier values at addresses 0 and 1 can be read (only address a 0 is used in this mode, all other address inputs are ignored). read status register (70h) this is one of the two commands that is executable while the state machine is operating. after this com- mand is written, a read of the device will output the contents of the status register, regardless of the ad- dress presented to the device. the device automatically enters this mode after pro- gram or erase has completed. clear status register (50h) the wsm can only set the program status and erase status bits in the status register, it can not clear them. two reasons exist for operating the status register in this fashion. the first is a synchro- nization. the wsm does not know when the host cpu has read the status register, therefore it would not know when to clear the status bits. secondly, if the cpu is programming a string of bytes, it may be more efficient to query the status register after pro- gramming the string. thus, if any errors exist while programming the string, the status register will return the accumulated error status. 13
a28f400bx-t/b program setup (40h or 10h) this command simply sets the cui into a state such that the next write will load the address and data registers. either 40h or 10h can be used for pro- gram setup. both commands are included to ac- commodate efforts to achieve an industry standard command code set. program the second write after the program setup command, will latch addresses and data. also, the cui initiates the wsm to begin execution of the program algo- rithm. while the wsm finishes the algorithm, the de- vice will output status register contents. note that the wsm cannot be suspended during program- ming. erase setup (20h) prepares the cui for the erase confirm command. no other action is taken. if the next command is not an erase confirm command then the cui will set both the program status and erase status bits of the status register to a ``1'', place the device into the read status register state, and wait for another command. erase confirm (d0h) if the previous command was an erase setup com- mand, then the cui will enable the wsm to erase, at the same time closing the address and data latches, and respond only to the read status register and erase suspend commands. while the wsm is exe- cuting, the device will output status register data when oe y is toggled low. status register data can only be updated by toggling either oe y or ce y low. erase suspend (b0h) this command only has meaning while the wsm is executing an erase operation, and therefore will only be responded to during an erase operation. after this command has been executed, the cui will set an output that directs the wsm to suspend erase operations, and then return to responding to only read status register or to the erase resume com- mands. once the wsm has reached the suspend state, it will set an output into the cui which allows the cui to respond to the read array, read status register, and erase resume commands. in this mode, the cui will not respond to any other com- mands. the wsm will also set the wsm status bit to a ``1''. the wsm will continue to run, idling in the suspend state, regardless of the state of all input control pins, with the exclusion of rp y .rp y will immediately shut down the wsm and the remainder of the chip. during a suspend operation, the data and address latches will remain closed, but the ad- dress pads are able to drive the address into the read path. erase resume (d0h) this command will cause the cui to clear the sus- pend state and set the wsm status bit to a ``0'', but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. 3.3.3 status register the 4-mbit boot block flash family contains a status register which may be read to determine when a pro- gram or erase operation is complete, and whether that operation completed successfully. the status register may be read at any time by writing the read status command to the cui. after writing this com- mand, all subsequent read operations output data from the status register until another command is written to the cui. a read array command must be written to the cui to return to the read array mode. the status register bits are output on dq [ 0:7 ] whether the device is in the byte-wide (x8) or word- wide (x16) mode. in the word-wide mode the upper byte, dq [ 8:15 ] is set to 00h during a read status command. in the byte-wide mode, dq [ 8:14 ] are tri- stated and dq 15 /a b 1 retains the low order address function. it should be noted that the contents of the status register are latched on the falling edge of oe y or ce y whichever occurs last in the read cycle. this prevents possible bus errors which might occur if the contents of the status register change while reading the status register. ce y or oe y must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. the status register is the interface between the mi- croprocessor and the write state machine (wsm). when the wsm is active, this register will indicate the status of the wsm, and will also hold the bits indicating whether or not the wsm was successful in performing the desired operation. the wsm sets status bits ``three'' through ``seven'' and clears bits ``six'' and ``seven'', but cannot clear status bits ``three'' through ``five''. these bits can only be cleared by the controlling cpu through the use of the clear status register command. 14
a28f400bx-t/b 3.3.3.1 status register bit definition table 4. status register definitions wsms ess es ps vpps r r r 76543210 notes: sr.7 e write state machine status 1 e ready 0 e busy write state machine status bit must first be checked to determine byte/word program or block erase comple- tion, before the program or erase status bits are checked for success. sr.6 e erase suspend status 1 e erase suspended 0 e erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to ``1''. ess bit re- mains set to ``1'' until an erase resume command is issued. sr.5 e erase status 1 e error in block erasure 0 e successful block erase when this bit is set to ``1''. wsm has applied the maxi- mum number of erase pulses to the block and is still unable to successfully perform an erase verify. sr.4 e program status 1 e error in byte/word program 0 e successful byte/word program when this bit is set to ``1'', wsm has attempted but failed to program a byte or word. sr.3 e v pp status 1 e v pp low detect; operation abort 0 e v pp ok the v pp status bit unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates the v pp level only after the byte write or block erase command sequences have been entered and informs the system if v pp has not been switched on. the v pp status bit is not guaranteed to report ac- curate feedback between v ppl and v pph . sr.2 sr.0 e reserved for future enhancements these bits are reserved for future use and should be masked out when polling the status register. 3.3.3.2 clearing the status register certain bits in the status register are set by the write state machine, and can only be reset by the system software. these bits can indicate various failure con- ditions. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in se- quence). the status register may then be read to determine if an error occurred during that program- ming or erasure series. this adds flexibility to the way the device may be programmed or erased. to clear the status register, the clear status register command is written to the cui. then, any other command may be issued to the cui. note again that before a read cycle can be initiated, a read array command must be written to the cui to specify whether the read data is to come from the array, status register, or intelligent identifier. 3.3.4 program mode program is executed by a two-write sequence. the program setup command is written to the cui fol- lowed by a second write which specifies the address and data to be programmed. the write state ma- chine will execute a sequence of internally timed events to: 1. program the desired bits of the addressed mem- ory word (byte), and 2. verify that the desired bits are sufficiently pro- grammed. programming of the memory results in specific bits within a byte or word being changed to a ``0''. if the user attempts to program ``1''s, there will be no change of the memory cell content and no error oc- curs. 15
a28f400bx-t/b similar to erasure, the status register indicates whether programming is complete. while the pro- gram sequence is executing, bit 7 of the status regis- ter is a ``0''. the status register can be polled by toggling either ce y or oe y to determine when the program sequence is complete. only the read status register command is valid while program- ming is active. when programming is complete, the status bits, which indicate whether the program operation was successful, should be checked. if the programming operation was unsuccessful, bit 4 of the status regis- ter is set to a ``1'' to indicate a program failure. if bit 3 is set then v pp was not within acceptable limits, and the wsm will not execute the programming se- quence. the status register should be cleared before at- tempting the next operation. any cui instruction can follow after programming is completed; however, it must be recognized that reads from the memory, status register, or intelligent identifier cannot be ac- complished until the cui is given the appropriate command. a read array command must first be giv- en before memory contents can be read. figure 6 shows a system software flowchart for de- vice byte programming operation. figure 7 shows a similar flowchart for device word programming oper- ation (a28f400bx-only). 3.3.5 erase mode erasure of a single block is initiated by writing the erase setup and erase confirm commands to the cui, along with the addresses a [ 12:17 ] , identifying the block to be erased. these addresses are latched internally when the erase confirm command is is- sued. block erasure results in all bits within the block being set to ``1''. the wsm will execute a sequence of internally timed events to: 1. program all bits within the block 2. verify that all bits within the block are sufficiently programmed 3. erase all bits within the block and 4. verify that all bits within the block are sufficiently erased while the erase sequence is executing, bit 7 of the status register is a ``0''. when the status register indicates that erasure is complete, the status bits, which indicate whether the erase operation was successful, should be checked. if the erasure operation was unsuccessful, bit 5 of the status register is set to a ``1'' to indicate an erase failure. if v pp was not within acceptable limits after the erase confirm command is issued, the wsm will not execute an erase sequence; instead, bits of the status register is set to a ``1'' to indicate an erase failure, and bit 3 is set to a ``1'' to identify that v pp supply voltage was not within acceptable limits. the status register should be cleared before at- tempting the next operation. any cui instruction can follow after erasure is completed; however, it must be recognized that reads from the memory array, status register, or intelligent identifier can not be ac- complished until the cui is given the appropriate command. a read array command must first be giv- en before memory contents can be read. figure 8 shows a system software flowchart for block erase operation. 3.3.5.1 suspending and resuming erase since an erase operation typically requires 1.5 to 3 seconds to complete, an erase suspend command is provided. this allows erase-sequence interruption in order to read data from another block of the mem- ory. once the erase sequence is started, writing the erase suspend command to the cui requests that the write state machine (wsm) pause the erase se- quence at a predetermined point in the erase algo- rithm. the status register must be read to determine when the erase operation has been suspended. at this point, a read array command can be written to the cui in order to read data from blocks other than that which is being suspended. the only other valid command at this time is the erase resume command or read status register operation. figure 9 shows a system software flowchart detail- ing the operation. 16
a28f400bx-t/b during erase suspend mode, the chip can go into a pseudo-standby mode by taking ce y to v ih and the active current is now a maximum of 10 ma. if the chip is enabled while in this mode by taking ce y to v il , the erase resume command can be issued to resume the erase operation. upon completion of reads from any block other than the block being erased, the erase resume com- mand must be issued. when the erase resume command is given, the wsm will continue with the erase sequence and complete erasing the block. as with the end of erase, the status register must be read, cleared, and the next instruction issued in or- der to continue. 3.3.6 extended cycling intel has designed extended cycling capability into its etox iii flash memory technology. the 4-mbit boot block flash family is designed for 1,000 pro- gram/erase cycles on each of the seven blocks. the combination of low electric fields, clean oxide pro- cessing and minimized oxide area per memory cell subjected to the tunneling electric field, results in very high cycling capability. 17
a28f400bx-t/b 290501 5 bus command comments operation write setup data e 40h program address e byte to be programmed write program data to be programmed address e byte to be programmed read status register data. toggle oe y or ce y to update status register standby check sr.7 1 e ready, 0 e busy repeat for subsequent bytes. full status check can be done after each byte or after a sequence of bytes. write ffh after the last byte programming operation to reset the device to read array mode. full status check procedure 290501 6 bus command comments operation standby check sr.3 1 e v pp low detect standby check sr.4 1 e byte program error sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.4 is only cleared by the clear status register command, in cases where multiple bytes are programmed before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. figure 6. automated byte programming flowchart 18
a28f400bx-t/b 290501 7 bus command comments operation write setup data e 40h program address e word to be programmed write program data to be programmed address e word to be programmed read status register data. toggle oe y or ce y to update status register standby check sr.7 1 e ready, 0 e busy repeat for subsequent words. full status check can be done after each word or after a sequence of words. write ffh after the last word programming operation to reset the device to read array mode. full status check procedure 290501 8 bus command comments operation standby check sr.3 1 e v pp low detect standby check sr.4 1 e word program error sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.4 is only cleared by the clear status register command, in cases where multiple words are programmed before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. figure 7. automated word programming flowchart 19
a28f400bx-t/b 290501 9 bus command comments operation write setup data e 20h erase address e within block to be erased write erase data e d0h address e within block to be erased read status register data. toggle oe y or ce y to update status register standby check sr.7 1 e ready, 0 e busy repeat for subsequent blocks. full status check can be done after each block or after a sequence of blocks. write ffh after the last block erase operation to reset the device to read array mode. full status check procedure 290501 10 bus command comments operation standby check sr.3 1 e v pp low detect standby check sr.4,5 both 1 e command sequence error standby check sr.5 1 e block erase error sr.3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.5 is only cleared by the clear status register command, in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. figure 8. automated block erase flowchart 20
a28f400bx-t/b 290501 11 bus command comments operation write erase data e b0h suspend read status register data. toggle oe y or ce y to update status register standby check sr.7 1 e ready standby check sr.6 1 e suspended write read array data e ffh read read array data from block other than that being erased. write erase resume data e d0h figure 9. erase suspend/resume flowchart 3.4 power consumption 3.4.1 active power with ce y at a logic-low level and rp y at a logic- high level, the device is placed in the active mode. the device i cc current is a maximum 65 ma at 10 mhz with ttl input signals. 3.4.2 automatic power savings automatic power savings (aps) is a low pwer fea- ture during active mode of operation. the 4-mbit family of products incorporate power reduction control (prc) circuitry which basically allows the de- vice to put itself into a low current state when it is not being accessed. after data is read from the memory array, prc logic controls the device's pow- er consumption by entering the aps mode where maximum i cc current is 3 ma and typical i cc current is 1 ma. the device stays in this static state with outputs valid until a new location is read. 3.4.3 standby power with ce y at a logic-high level (v ih ), and the cui in read mode, the memory is placed in standby mode where the maximum i cc standby current is 100 m a with cmos input signals. the standby operation dis- ables much of the device's circuitry and substantially reduces device power consumption. the outputs (dq [ 0:15 ] or dq [ 0:7 ] ) are placed in a high-imped- ance state independent of the status of the oe y signal. when the 4-mbit boot block flash family is deselected during erase or program functions, the devices will continue to perform the erase or pro- gram function and consume program or erase active power until program or erase is completed. 21
a28f400bx-t/b 3.4.4 deep powerdown the 4-mbit boot block flash family has a rp y pin which places the device in the deep powerdown mode. when rp y is at a logic-low (gnd g 0.2v), all circuits are turned off and the device typically draws a maximum 80 m aofv cc current. during read modes, the rp y pin going low dese- lects the memory and places the output drivers in a high impedance state. recovery from the deep pow- er-down state, requires a minimum of 300 ns to ac- cess valid data (t phqv ). during erase or program modes, rp y low will abort either erase or program operation. the contents of the memory are no longer valid as the data has been corrupted by the rp y function. as in the read mode above, all internal circuitry is turned off to achieve the low current level. rp y transitions to v il or turn- ing power off to the device will clear the status regis- ter. this use of rp y during system reset is important with automated write/erase devices. when the sys- tem comes out of reset it expects to read from the flash memory. automated flash memories provide status information when accessed during write/ erase modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization would not occur because the flash memory would be providing the status information instead of array data. intel's flash memories allow proper cpu initialization fol- lowing a system reset through the use of rp y input. in this application rp y is controlled by the same reset y signal that resets the system cpu. 3.5 power-up operation the 4-mbit boot block flash family is designed to offer protection against accidental block erasure or programming during power transitions. upon power- up the 4-mbit boot block flash family is indifferent as to which power supply, v pp or v cc , powers-up first. power supply sequencing is not required. the 4-mbit boot block flash family ensures the cui is reset to the read mode on power-up. in addition, on power-up the user must either drop ce y low or present a new address to ensure valid data at the outputs. a system designer must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we y and ce y must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides an added level of protection since alteration of mem- ory contents can only occur after successful com- pletion of the two-step command sequences. finally the device is disabled until rp y is brought to v ih , regardless of the state of its control inputs. this fea- ture provides yet another level of memory protec- tion. 3.6 power supply decoupling flash memory's power switching characteristics re- quire careful device decoupling methods. system designers are interested in 3 supply current issues: # standby current levels (i ccs ) # active current levels (i ccr ) # transient peaks produced by falling and rising edges of ce y . transient current magnitudes depend on the device outputs' capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 m f ceramic capacitor connected between each v cc and gnd, and be- tween its v pp and gnd. these high frequency, low- inherent inductance capacitors should be placed as close as possible to the package leads. 3.6.1 v pp trace on printed circuit boards writing to flash memories while they reside in the target system, requires special consideration of the v pp power supply trace by the printed circuit board designer. the v pp pin supplies the flash memory cells current for programming and erasing. one should use similar trace widths and layout consider- ations given to the v cc power supply trace. ade- quate v pp supply traces and decoupling will de- crease spikes and overshoots. 3.6.2 v cc ,v pp and rp y transitions the cui latches commands as issued by system software and is not altered by v pp or ce y tran- sitions or wsm actions. its state upon power-up, af- ter exit from deep power-down mode or after v cc transitions below v lko (lockout voltage), is read array mode. after any word/byte write or block erase operation is complete and even after v pp transitions down to v ppl , the cui must be reset to read array mode via the read array command when accesses to the flash memory are desired. 22
a28f400bx-t/b absolute maximum ratings * operating temperature during read b 40 cto a 125 c during block erase and word/byte write b 40 cto a 125 c temperature under bias b 40 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin (except v cc ,v pp ,a 9 and rp y ) with respect to gnd b 2.0v to a 7.0v (2) voltage on pin rp y or pin a 9 with respect to gnd b 2.0v to a 13.5v (2, 3) v pp program voltage with respect to gnd during block erase and word/byte write b 2.0v to a 14.0v (2, 3) v cc supply voltage with respect to gnd b 2.0v to a 7.0v (2) output short circuit current100 ma (4) notice: this data sheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest data sheet be- fore finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc voltage is b 0.5v on input/output pins. during transitions, this level may undershoot to b 2.0v for periods k 20 ns. maximum dc voltage on input/output pins is v cc a 0.5v which, during transitions, may overshoot to v cc a 2.0v for periods k 20 ns. 3. maximum dc voltage on v pp may overshoot to a 14.0v for periods k 20 ns. maximum dc voltage on rp y or a 9 may overshoot to 13.5v for periods k 20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. operating conditions symbol parameter notes min max units t a operating temperature b 40 125 c v cc v cc supply voltage (10%) 5 4.40 5.50 v dc characteristics symbol parameter notes min typ max unit test condition i li input load current 1 g 1.0 m av cc e v cc max v in e v cc or gnd i lo output leakage current 1 g 10 m av cc e v cc max v out e v cc or gnd 23
a28f400bx-t/b dc characteristics (continued) symbol parameter notes min typ max unit test condition i ccs v cc standby current 1, 3 1.5 ma v cc e v cc max ce y e rp y e v ih 130 m av cc e v cc max ce y e rp y e v cc g 0.2v 28f200bx: byte y e v cc g 0.2v or gnd i ccd v cc deep powerdown current 1 80 m arp y e gnd g 0.2v i ccr v cc read current for 1, 5, 60 ma v cc e v cc max, ce y e gnd 28f400bx byte-wide 6 f e 10 mhz, i out e 0ma and word-wide mode cmos inputs 65 ma v cc e v cc max, ce y e v il f e 10 mhz, i out e 0ma ttl inputs i ccw v cc word/byte write current 1, 4 65 ma word write in progress i cce v cc block erase current 1,4 30 ma block erase in progress i cces v cc erase suspend current 1, 2 5 10 ma block erase suspended, ce y e v ih i pps v pp standby current 1 g 15 m av pp s v cc i ppd v pp deep powerdown current 1 5.0 m arp y e gnd g 0.2v i ppr v pp read current 1 200 m av pp l v cc i ppw v pp word write current 1, 4 40 ma v pp e v pph word write in progress i ppw v pp byte write current 1, 4 30 ma v pp e v pph byte write in progress i ppe v pp block erase current 1, 4 30 ma v pp e v pph block erase in progress i ppes v pp erase suspend current 1 200 m av pp e v pph block erase suspended i rp y rp y current 1, 4 500 m arp y e v hh i id a 9 intelligent identifier current 1, 4 500 m aa 9 e v id v id a 9 intelligent identifier voltage 11.5 13.0 v v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 v cc a 0.5 v v ol output low voltage 0.45 v v cc e v cc min i ol e 5.8 ma 24
a28f400bx-t/b dc characteristics (continued) symbol parameter notes min typ max unit test condition v oh output high voltage 2.4 v v cc e v cc min i oh eb 2.5 ma v ppl v pp during normal operations 3 0.0 6.5 v v pph v pp during erase/write operations 7 11.4 12.0 12.6 v v lko v cc erase/write lock voltage 2.0 v v hh rp y unlock voltage 11.5 13.0 v boot block write/erase capacitance (4) t a e 25 c, f e 1 mhz symbol parameter typ max unit condition c in input capacitance 6 8 pf v in e 0v c out output capacitance 10 12 pf v out e 0v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc e 5.0v, v pp e 12.0v, t e 25 c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device deselected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases and word/byte writes are inhibited when v pp e v ppl and not guaranteed in the range between v pph and v ppl . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to less than 1 ma typical in static operation. 6. cmos inputs are either v cc g 0.2v or gnd g 0.2v. ttl inputs are either v il or v ih . 7. v pp e 12.0v g 5% for applications requiring 1,000 block erase cycles. standard test configuration standard ac input/output reference waveform 290501 12 ac test inputs are driven at v oh (2.4 v ttl ) for a logic ``1'' and v ol (0.45 v ttl ) for a logic ``0''. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) k 10 ns. standard ac testing load circuit 290501 13 c l e 100 pf c l includes jig capacitance r l e 3.3 k x 25
a28f400bx-t/b ac characteristicseread only operations (1) versions a28f400bx-90 (4, 5) unit symbol parameter notes min max t avav t rc read cycle time 90 ns t avqv t acc address to 90 ns output delay t elqv t ce ce y to output delay 90 ns t phqv t pwh rp y high to 300 ns output delay t glqv t oe oe y to output delay 2 45 ns t elqx t lz ce y to output low z 0 ns t ehqz t hz ce y high to output 35 ns high z t glqx t olz oe y to output low z 3 0 ns t ghqz t df oe y high to output 3 35 ns high z t oh output hold from 3 0 ns addresses, ce y or oe y change, whichever is first t elfl ce y to byte y 35ns t elfh switching low or high t fhqv byte y switching 3, 5 90 ns high to valid output delay t flqz byte y switching 3 35 ns low to output high z notes: 1. see ac input/output reference waveform for timing measurements. 2. oe y may be delayed up to t ce t oe after the falling edge of ce y without impact on t ce . 3. sampled, not 100% tested. 4. see standard test configuration. 5. t flqv , byte y switching low to valid output delay, will be equal to t avqv from the time dq 15 /a b 1 becomes valid. 26
a28f400bx-t/b figure 10. ac waveforms for read operations 290501 14 27
a28f400bx-t/b figure 11. byte y timing diagram for both read and write operations for a28f400bx 290501 15 28
a28f400bx-t/b ac characteristicsewe y controlled write operations (1) versions (4) a28f400bx-90 (9) unit symbol parameter notes min max t avav t wc write cycle time 90 ns t phwl t ps rp y high recovery to 210 ns we y going low t elwl t cs ce y setup to we y going low 0 ns t phhwh t phs rp y v hh setup to we y 6, 8 100 ns going high t vpwh t vps v pp setup to we y going high 5, 8 100 ns t avwh t as address setup to we y 360 ns going high t dvwh t ds data setup to we y going high 4 60 ns t wlwh t wp we y pulse width 60 ns t whdx t dh data hold from we y high 4 0 ns t whax t ah address hold from we y high 3 10 ns t wheh t ch ce y hold from we y high 10 ns t whwl t wph we y pulse width high 30 ns t whqv1 duration of word/byte 2, 5 7 m s programming operation t whqv2 duration of erase operation (boot) 2, 5, 6 0.4 s t whqv3 duration of erase operation 2, 5 0.4 s (parameter) t whqv4 duration of erase operation (main) 2, 5 0.7 s t qwl t vph v pp hold from valid srd 5, 8 0 ns t qvph t phh rp y v hh hold from valid srd 6, 8 0 ns t phbr boot-block relock delay 7, 8 100 ns 29
a28f400bx-t/b ac characteristicsewe y controlled write operations (1) (continued) notes: 1. read timing characteristics during write and erase operations are the same as during read-only operations. refer to ac characteristics during read mode. 2. the on-chip wsm completely automates program/erase operations; program/erase algorithms are now controlled inter- nally which includes verify and margining operations. 3. refer to command definition table for valid a in . 4. refer to command definition table for valid d in . 5. program/erase durations are measured to valid srd data (successful operation, sr.7 e 1). 6. for boot block program/erase, rp y should be held at v hh until operation completes successfully. 7. time t phbr is required for successful relocking of the boot block. 8. sampled but not 100% tested. 9. see standard test configuration. block erase and word/byte write performance v pp e 12.0v g 5% parameter notes a28f400bx-90 unit min typ (1) max boot/parameter 2 1.5 10.5 s block erase time main block 2 3.0 18 s erase time main block byte 2 1.4 5.0 s program time main block word 2 0.7 2.5 s program time notes: 1. 25 c 2. excludes system-level overhead. 30
a28f400bx-t/b figure 12. ac waveforms for a write and erase operations (we y -controlled writes) 290501 16 31
a28f400bx-t/b ac characteristicsece y -controlled write operations (1, 9) versions a28f400bx-90 (10) unit symbol parameter notes min max t avav t wc write cycle time 90 ns t phel t ps rp y high recovery to ce y going low 210 ns t wlel t ws we y setup to ce y going low 0 ns t phheh t phs rp y v hh setup to ce y going high 6, 8 100 ns t vpeh t vps v pp setup to ce y going high 5, 8 100 ns t aveh t as address setup to ce y going high 3 60 ns t dveh t ds data setup to ce y going high 4 60 ns t eleh t cp ce y pulse width 60 ns t ehdx t dh data hold from ce y high 4 0 ns t ehax t ah address hold from ce y high 3 10 ns t ehwh t wh we y hold from ce y high 10 ns t ehel t cph ce y pulse width high 30 ns t ehqv1 duration of word/byte programming 2, 5 7 m s operation t ehqv2 duration of erase operation (boot) 2, 5, 6 0.4 s t ehqv3 duration of erase operation (parameter) 2, 5 0.4 s t ehqv4 duration of erase operation (main) 2, 5 0.7 s t qwl t vph v pp hold from valid srd 5, 8 0 ns t qvph t phh rp y v hh hold from valid srd 6, 8 0 ns t phbr boot-block relock delay 7 100 ns notes: 1. chip-enable controlled writes: write operations are driven by the valid combination of ce y and we y in systems where ce y defines the write pulse-width (within a longer we y timing waveform), all set-up, hold and inactive we y times should be measured relative to the ce y waveform. 2, 3, 4, 5, 6, 7, 8: refer to ac characteristics for we y -controlled write operations. 9. read timing characteristics during write and erase operations are the same as during read-only operations. refer to ac characteristics during read mode. 10. see standard test configuration. 32
a28f400bx-t/b figure 13. alternate ac waveforms for write and erase operations (ce y -controlled writes) 290501 17 33
a28f400bx-t/b ordering information 290501 18 valid combinations: ab28f400bx-t90 ab28f400bx-b90 additional information order number a28f200bx datasheet 290500 28f200bx/28f002bx datasheet 290448 28f200bx-l/28f002bx-l datasheet 290449 28f400bx-l/28f004bx-l datasheet 290450 ap-363 ``extended flash bios design for portable computers'' 292098 er-28 ``etox tm iii flash memory technology'' 204012 er-29 ``the intel 2/4-mbit boot block flash memory family'' 294013 revision history number description 002 changed package designator 003 changed i pps to 15 m a 34

▲Up To Search▲

Price & Availability of A28F400BX-B

	To Download A28F400BX-B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .